1. Field of Invention
Embodiments of the present invention relate to fault testing in electronic circuits. More particularly, the embodiments of the present invention relate to programmable in-situ launch and capture clock generation for at-speed testing.
2. Description of the Background Art
Investigating faults in semiconductor devices is a critical aspect of the manufacturing and maintenance process. As the geometries of semiconductor devices are getting smaller, failures caused by defects in the manufacturing process and design margins are becoming increasingly common. Exemplary failures include those caused by timing-related at-speed faults.
Conventional methods of fault testing, such as stuck-at fault models, etc., are no longer an effective solution. A better method is at-speed testing, i.e., testing the device at its working frequency. At-speed testing is based on a transition fault model and/or a path delay fault model. These models require a device tester to launch the test pattern and capture the response of the device at the operating speed. The functional mode of the at-speed device tester produces two pulses known as a launch clock and a capture clocks. At-speed testing depends on these two clocks to detect at-speed-related defects.
However, maintaining the accuracy of these clocks at higher clock speeds is very costly and difficult. Most often, the device tester's at-speed frequency performance does not scale up with the increasing speed of the device's internal operating frequency. To combat this problem, existing test generation tools use on-chip high-speed test clocks. This is also known as in-situ test clock generation. However, existing test clock generation techniques are not applicable across different technologies, since it is difficult to scale the delay of the clock according to the device requirement. This reduces the accuracy of testing these devices. Moreover, these techniques do not address critical path delay measurement.